This invention relates to tools for analyzing integrated circuit fabrication processes; and more particularly, it relates to tools for detecting the presence of any flaw in a process which causes A-C defects.
Basically, an integrated circuit is comprised of a semiconductor substrate on which about a dozen layers of different materials, that have intricate microscopic patterns, are disposed on top of one another in a stack. To build this stack, many complex fabrication steps need to be sequentially performed. As one example of the details of those steps and a representative integrated circuit fabrication process, see pages 428-431 of the textbook "Silicon Processing For The VLSI Era" Volume 2 by Stanley Wolf, Lattice Press of Sunset Beach, Calif., Copyright 1990.
If the integrated circuit fabrication steps could be performed in an ideal fashion, each layer in the stack would have uniform physical characteristics at all points across the substrate. However, absolute uniformity is impossible to achieve. Consequently, the circuits which are made from the stack of layers vary in their physical structure; and some of those variances cause differences in the speed of which the circuits operate.
In a normal integrated circuit fabrication process, the respective speeds of the circuits that are produced fall within some predefined allowable range. This allowable range can be defined for example as T.sub.AVE .+-.4.5 .sigma. where T.sub.AVE is an average delay and where .sigma. is one standard deviation. Any circuit which has a signal propagation delay that is too slow to be acceptable is herein defined to have an A-C defect.
Typically, the layers in an integrated circuit form hundreds of thousands of transistors which are interconnected along ten's of thousands of signal paths. This, in fact, occurs in any digital application specific integrated circuit (ASIC). For such circuits, to test every signal path for an A-C defect is impossible.
One practical reason for not testing every signal path is that such testing is too time consuming and thus too expensive, due to the large number of paths. Also, a conventional integrated circuit tester simply sends a set of input signals to a circuit under test and then after a fixed time interval measures the response of the circuit. Thus, a circuit which responds too slowly but with the correct output signals within the fixed time interval will pass the test.
This then presents a real dilemma because if a circuit with an A-C defect is incorporated into an electronic unit that is sold to a customer, the signal path with the A-C defect could cause an error when that signal path is activated. However, if the signal path with the A-C defect is only activated once in a while and at random time instants, then the source of the error is very difficult to identify and correct.